The phyCORE-i.MX7 development kit includes a PEB-D-RPI Expansion Board designed to facilitate the easy evaluation of certain interfaces available on the kit. The following sections will detail how to use these features in the environments in which they are supported. These instructions assume that you have a properly connected Expansion Board (included with your kit) and have booted into a supported environment (U-Boot and/or Linux) using BSP version PD18.2.0 or newer. If you are looking for information regarding Raspberry Pi HAT support, please see Raspberry Pi HAT.

See the end of this guide for further information about the configuration of signals that get passed to the PEB_D_RPI Expansion Board. 

PEB-D-RPI Expansion Board Interfaces


Use the following image as a reference for the connector interfaces on the PEB-D-RPI Expansion Board used in this document.

USB to Serial UART Interface


The phyCORE-i.MX7 is already configured by default to use UART1 for console input and output over the PEB-D-RPI Expansion Board's X6 micro-USB connector. This connector allows for the use of both UART1 and UART2 for serial data, however only UART1 is configured in the BSP by default because UART2 is reserved for the M4 core in PHYTEC's FreeRTOS software.

4KB EEPROM


This Expansion Board allows you to use the I2C4 interface to write and read small amounts of persistent data to and from an on-board EEPROM. The EEPROM is registered under the 'i2c4' node in the Expansion Board Linux device tree file 'imx7-peb-d-rpi.dtsi' and is accessible as a file in Linux's sysfs directory structure.

  • To write to and read from the 4KB EEPROM on the Expansion Board, run the following commands on the target:

    Target (Linux)

    echo 'Testing EEPROM!!' > /sys/class/i2c-dev/i2c-3/device/3-0056/eeprom
    hexdump -c -n 16 /sys/class/i2c-dev/i2c-3/device/3-0056/eeprom
    CODE
  • You should see the values you wrote to the EEPROM displayed on your console in hexdump format.

Buttons


The buttons S1 and S2 serve as an example of using GPIO pins as inputs to facilitate user input. The two buttons are registered under their own node, 'phytec_buttons', in the Expansion Board Linux device tree file 'imx7-peb-d-rpi.dtsi' and their status is accessible in Linux's debugfs directory structure. 

  • Use the following command to read the state of the buttons S1 and S2 on the PED-D-RPI Expansion Board

    Target (Linux)

    cat /sys/kernel/debug/gpio | grep "pebdrpi_button"
    CODE
  • You should see the current state of the GPIO pins connected to the active-low buttons displayed on your console.
  • Use the above command again while pressing and holding either of the buttons and notice that the state is now pulled high.

LEDs


The LEDs D1 and D2 serve as an example of using GPIO pins as outputs to control a device or devices. The two LEDs are registered under their own node, 'phytec_leds', in the Expansion Board Linux device tree file 'imx7-peb-d-rpi.dtsi' and their status and control are accessible in Linux's sysfs directory structure.

  • To turn the LEDs on and off, run the following commands on the target:

    Target (Linux)

    echo 0 > /sys/class/leds/pebdrpi_led_1/brightness
    echo 1 > /sys/class/leds/pebdrpi_led_1/brightness
    echo 0 > /sys/class/leds/pebdrpi_led_2/brightness
    echo 1 > /sys/class/leds/pebdrpi_led_2/brightness
    CODE
  • You should see the individual LEDs turn off and on based upon which LED you echoed.
  • If you would like to impress your friends or co-workers with your technical prowess...

     Make an LED light show!
    • Open a text editor to write a script: 

      Target (Linux)

      vi ~/lightShow.sh
      CODE
    • Enter the following and save the file: 

      Vi Text Editor

      #!/bin/bash
      
      for i in `seq 1 20`; do
      	echo 0 > /sys/class/leds/pebdrpi_led_1/brightness
      	echo 1 > /sys/class/leds/pebdrpi_led_2/brightness
      	sleep 0.5
      	echo 1 > /sys/class/leds/pebdrpi_led_1/brightness
      	echo 0 > /sys/class/leds/pebdrpi_led_2/brightness
      	sleep 0.5
      done
      echo 0 > /sys/class/leds/pebdrpi_led_1/brightness
      CODE

      The vi text editor begins in "Command Mode" and you must first hit the 'i' key in order to enter "Insert Mode". Using the arrow keys to navigate, make the necessary changes and then hit ESC to go back to "Command mode". Now enter ":wq" to write the file and quit.


      Pro Tip: Use the right click on your mouse to paste. This will only work if you are in "Insert Mode" first.

    • Change the permissions in order to execute the script: 

      Target (Linux)

      chmod +x ~/lightShow.sh
      CODE
    • Now run the script in the background: 

      Target (Linux)

      ~/lightShow.sh &
      CODE
    • The light show will end automatically after approximately 20 seconds. To end it early you can enter the following command: 

      Target (Linux)

      killall lightShow.sh
      CODE

Raspberry Pi-compatible 40-pin Header


The header X11 provides Raspberry Pi HAT hardware support and a convenient location to connect to GPIO or other interface signals that are routed to the Expansion Board. If you are looking for information regarding Raspberry Pi HAT support, please see Raspberry Pi HAT.

GPIO and Interface Signals Map

The following tables show the GPIO bank, pins, and Raspberry Pi-compatible interface signals mapped to the 40-pin header on the PEB-D-RPI Expansion Board:

GPIOs
Pin FunctionPin NumberPin Function
VCC_3V3MEM12VDD_5V0
I2C1_SDA34VDD_5V0
I2C1_SCL56GND
GPIO4_IO2178GPIO4_IO5
GND910GPIO4_IO4
GPIO4_IO201112GPIO5_IO15
GPIO4_IO221314GND
GPIO4_IO231516GPIO1_IO15
VCC_3V3MEM1718GPIO1_IO14
GPIO6_IO201920GND
GPIO6_IO192122GPIO5_IO11
GPIO6_IO212324GPIO6_IO22
GND2526GPIO5_IO9
I2C4_SDA2728I2C4_SCL
GPIO5_IO142930GND
GPIO1_IO023132GPIO5_IO13
GPIO4_IO183334GND
GPIO5_IO163536GPIO4_IO19
GPIO4_IO163738GPIO4_IO17
GND3940GPIO5_IO17
Interface Signals
Pin FunctionPin NumberPin Function
VCC_3V3MEM12VDD_5V0
I2C1_SDA34VDD_5V0
I2C1_SCL56GND
SPI2_MOSI78UART3_TX
GND910UART3_RX
SPI2_SCLK1112SAI2_TX_BCLK
SPI2_MISO1314GND
SPI2_SS01516GPIO1_IO15
VCC_3V3MEM1718GPIO1_IO14
SPI3_MOSI1920GND
SPI3_MOSI2122GPIO5_IO11
SPI3_SCLK2324SPI3_SS0
GND2526SPI3_SS2
I2C4_SDA2728I2C4_SCL
GPIO5_IO142930GND
PWM2_OUT3132SAI2_RX_BCLK
SPI1_MISO3334GND
SAI2_TX_SYNC3536SPI1_SS0
SPI1_SCLK3738SPI1_MOSI
GND3940SAI2_TX_DATA0

The pin functions highlighted in blue are fixed and can not or should not be changed.

Jumpers

The 40-pin header also utilizes soldered jumpers to toggle the selection of specific Raspberry Pi-compatible interface signals to certain pins, enabling support of different Raspberry Pi HATs. The following table details the pins and signals that the jumpers control:

JumperPinDefault Signal (position 1+2)Alternative Signal (position 2+3)
J531PWM2_OUTSAI2_TX_BCLK
J633SPI1_MISOSAI2_TX_SYNC
J735SD2_DATA2SPI1_MISO
J837SPI1_SCLKSAI2_TX_DATA0
J940SD2_DATA3SPI1_SCLK
J1012SD2_DATA1PWM2_OUT
J1129GPIO5_IO14SPI1_MOSI
J1238SPI1_MOSIGPIO5_IO14

Toggling GPIOs Connected to 40-pin Header

When a Raspberry Pi HAT isn't connected, you can use PHYTEC's RPi.GPIO Python library (included with BSP version PD18.2.0 or later) to control GPIOs connected to the 40-pin header. By default, only the following pins are configured for GPIO use in the PEB-D-RPI device tree file: 7, 11, 12, 13, 15, 16, 18, 22, 29, 32, 35, 40. For information on how to enable more GPIOs, please reference Raspberry Pi HAT.

To set pin 7 on the 40-pin header to be a GPIO output and toggle its value, open your Python interpreter by using the following command: 

Target (Linux)

python
CODE

Now in the Python Interpreter, enter the following:

Target (Python Interpreter)

import RPi.GPIO as GPIO
GPIO.setmode(GPIO.BOARD)
GPIO.setup(7, GPIO.OUT)
GPIO.output(7, GPIO.HIGH)
GPIO.output(7, GPIO.LOW)
GPIO.cleanup()
exit()
PY

Using a digital multimeter or other suitable device (such as an LED), you can see the value on pin 7 of the 40-pin header go from 0 to 3.3 V and back to 0 V using the above code. You can also toggle GPIOs using the libgpiod utilities installed to the BSP file system. To toggle the same pin using libgpiod utilities, run the following commands on the target:

Target (Linux)

gpioset 3 21=1
gpioset 3 21=0
CODE

The above commands toggle GPIO chip 4, pin 21, which is routed to pin 7 of the 40-pin header on the PEB-D-RPI Expansion Board.

ARM JTAG 20-pin Debug Interface Header


The header X5 allows you to connect an ARM JTAG 20-pin compatible debugger to the phyCORE-i.MX7. PHYTEC has tested the JTAG interface using an ARM DSTREAM debugger with ARM DS-5 Development Studio and has also verified functionality using a J-Link Debugger Probe with SEGGER's Ozone Debugging Software. You will need to reference the documentation provided by the manufacturer of your debugger to configure and connect your debugger to the debug header. For more information about JTAG see JTAG

Un-populated Expansion Signal Pin Headers


The un-populated headers X12 and X13 can be used to access Expansion Board signals that are not brought out to the Raspberry Pi-compatible 40-pin header. The following tables show the signals brought out to the un-populated headers:

Connector X12
SignalPin NumberSignal
VCC_3V3MEM12VDD_5V0
GND34GND
SD2_DATA056SD2_DATA3
SD2_DATA178SD2_CLK
SD2_DATA2910SD2_CMD
SPI1_MISO1112SPI1_MOSI
GND1314GND
UART7_TX1516UART7_RX
UART7_RTS1718UART7_CTS
SPI1_SCLK1920SPI1_SS0
X_POR_B2122GND
X_SPI3_MISO2324X_SPI3_SCLK
X_SPI3_MOSI2526X_SPI3_SS0
GND2728GND
X_SD2_CD_B2930X_PWM2
X_SD2_WP3132X_CAN2_TX
X_RD2_RESET_B3334X_CAN2_RX
X_MX7_ONOFF3536X_PMIC_PWRON
GND3738GND
X_UART1_TX3940X_UART3_TX
X_UART1_RX4142X_UART3_RX
X_UART2_TX4344X_UART6_TX
X_UART2_RX4546X_UART6_RX
GND4748GND
Connector X13
SignalPin NumberSignal
VCC_3V3MEM12VDD_5V0
X_I2C4_SDA34X_SNVS_TAMPER0
X_I2C4_SCL56GND
GND78X_GPIO2_30
X_NAND_CE1_B910X_NAND_CE2_B
X_NAND_CE0_B1112X_NAND_CE3_B
X_NAND_DQS1314X_NAND_READY_B
X_NAND_WP_B1516GND
GND1718EXP_CONN_MUX7
EXP_CONN_MUX11920EXP_CONN_MUX8
EXP_CONN_MUX22122EXP_CONN_MUX9
EXP_CONN_MUX32324GND
GND2526EXP_CONN_MUX10
EXP_CONN_MUX42728EXP_CONN_MUX11
EXP_CONN_MUX52930EXP_CONN_MUX12
EXP_CONN_MUX63132GND
GND3334X_GPIO2_10
X_ADC_IN03536X_GPIO2_11
X_ADC_IN13738X_GPIO2_12
X_ADC_IN23940X_GPIO2_13
X_ADC_IN34142X_GPIO2_14
GND4344

GND

X_USB_H_DATA4546X_MDIO_D
X_USB_H_STROBE4748X_MDIO_CLK


 Advanced Signal Configurations

The expansion connector X16 on the phyBOARD-i.MX7 Carrier Board provides a way to implement custom expansion boards for extended functionality and development. Standard interfaces such as UART, SPI, I2C, and various GPIO are available at the expansion connector and therefore are accessible on the PEB-D-RPI Expansion Board on the phyCORE-i.MX7 development kit. 

Due to the small footprint of the solder jumpers, we recommend using caution when modifying these. Please contact our sales team if you require any options beyond the default configuration.

There are 12 jumpers on the phyBOARD-i.MX7 development kit that are comprised of four solder pads, which provide the option of routing the RGMII2 signals out to the expansion connector rather than to the phyBOARD-i.MX7 Carrier Board's Ethernet PHY.

J9-J20.png

J9

1+2, 3+4

(Default)

X_RGMII2_RXD0 is routed to the ETH2 phy.

X_SNVS_TAMPER1 is routed to the expansion connector at EXP_CONN_MUX1.

2+3

X_RGMII2_RXD0 is routed to the expansion connector at EXP_CONN_MUX1.

X_SNVS_TAMPER1 is not connected to the expansion connector.


J10

1+2, 3+4

(Default)

X_RGMII2_RXD1 is routed to the ETH2 phy.

X_SNVS_TAMPER2 is routed to the expansion connector at EXP_CONN_MUX2.

2+3

X_RGMII2_RXD1 is routed to the expansion connector at EXP_CONN_MUX2.

X_SNVS_TAMPER2 is not connected to the expansion connector.


J11

1+2, 3+4

(Default)

X_RGMII2_RXD2 is routed to the ETH2 phy.

X_SD1_RESET_B is routed to the expansion connector at EXP_CONN_MUX3.

2+3

X_RGMII2_RXD2 is routed to the expansion connector at EXP_CONN_MUX3.

X_SD1_RESET_B is not connected to the expansion connector.


J12

1+2, 3+4

(Default)

X_RGMII2_RXD3 is routed to the ETH2 phy.

X_GPIO1_O9 is routed to the expansion connector at EXP_CONN_MUX4.

2+3

X_RGMII2_RXD3 is routed to the expansion connector at EXP_CONN_MUX4.

X_GPIO1_09 is not connected to the expansion connector.


J13

1+2, 3+4

(Default)

X_RGMII2_RX_CTL is routed to the ETH2 phy.

X_GPIO2_15 is routed to the expansion connector at EXP_CONN_MUX5.

2+3

X_RGMII2_RX_CTL is routed to the expansion connector at EXP_CONN_MUX5.

X_GPIO2_15 is not connected to the expansion connector.


J14

1+2, 3+4

(Default)

X_RGMII2_RXC is routed to the ETH2 phy.

X_LCD1_RESET is routed to the expansion connector at EXP_CONN_MUX6.

2+3

X_RGMII2_RXC is routed to the expansion connector at EXP_CONN_MUX6.

X_LCD1_RESET is not connected to the expansion connector.


J15

1+2, 3+4

(Default)

X_RGMII2_TXD0 is routed to the ETH2 phy.

X_X_I2C1_SCL is routed to the expansion connector at EXP_CONN_MUX7.

2+3

X_RGMII2_TXD0 is routed to the expansion connector at EXP_CONN_MUX7.

X_I2C1_SCL is not connected to the expansion connector.


J16

1+2, 3+4

(Default)

X_RGMII2_TXD1 is routed to the ETH2 phy.

X_I2C1_SDA is routed to the expansion connector at EXP_CONN_MUX8.

2+3

X_RGMII2_TXD1 is routed to the expansion connector at EXP_CONN_MUX8.

X_I2C1_SDA is not connected to the expansion connector.


J17

1+2, 3+4

(Default)

X_RGMII2_TXD2 is routed to the ETH2 phy.

X_RGMII1_RX_CTL is routed to the expansion connector at EXP_CONN_MUX9.

2+3

X_RGMII2_TXD2 is routed to the expansion connector at EXP_CONN_MUX9.

X_RGMII1_RX_CTL is not connected to the expansion connector.


J18

1+2, 3+4

(Default)

X_RGMII2_TXD3 is routed to the ETH2 phy.

X_RGMII1_RXC is routed to the expansion connector at EXP_CONN_MUX10.

2+3

X_RGMII2_RXD3 is routed to the expansion connector at EXP_CONN_MUX10.

X_RGMII1_RXC is not connected to the expansion connector.


J19

1+2, 3+4

(Default)

X_RGMII2_TX_CTL is routed to the ETH2 phy.

X_RGMII1_TX_CTL is routed to the expansion connector at EXP_CONN_MUX11.

2+3

X_RGMII2_TX_CTL is routed to the expansion connector at EXP_CONN_MUX11.

X_RGMII1_TX_CTL is not connected to the expansion connector.


J20

1+2, 3+4

(Default)

X_RGMII2_TXC is routed to the ETH2 phy.

X_RGMII1_TXC is routed to the expansion connector at EXP_CONN_MUX12.

2+3

X_RGMII2_TXC is routed to the expansion connector at EXP_CONN_MUX12.

X_RGMII1_TXC is not connected to the expansion connector.

RGMII requirements should be considered when interfacing with RGMII2 via the expansion connector. It is recommended to verify all of the necessary timing budget parameters, such as trace length matching and skew/delay between clock and data, will meet the RGMII timing specifications.