The phyCORE-i.MX7 development kit provides a system power button at S2 (PWR). Pressing the S2 button will drive X_MX7_ONOFF low, which provides some control of various transitions between the power modes of the phyCORE-i.MX7.
- Holding the power button for a 'long press' (longer than ~5 seconds) while the phyCORE-i.MX7 is in the RUN mode will transition the module to the low power SNVS mode.
- Without a proper software shutdown, a long press may result in file system corruption as power is reduced to only the SNVS domain (RTC and tamper detection).
- When possible it is advised to initiate an OS controlled shutdown before removing power. In Linux, a 'poweroff' or 'shutdown' command will safely shut down the system, allowing subsequent safe removal of power.
- A short press of the power button while the phyCORE-i.MX7 is in RUN mode will not trigger any power events or transitions.
- When in SNVS mode, a short press of the button will transition the phyCORE-i.MX7 back to RUN mode and turn ON the board.
If an application requires direct power up without the use of a power button, then it is recommend to refer to the following PHYTEC application note: https://wiki.phytec.com/display/public/PRODUCTINFO/Application+Note%3A+Boot+i.MX7+without+pressing+the+power+button
Refer to the phyCORE-i.MX7 Reference Manual and datasheet for detailed information regarding the power modes and transitions.
A supervisory circuit is implemented at U6 to reset the system by monitoring the reset button (S3), software resets, and the main input voltage level. Either pressing the S3 reset button or triggering a software reset via the X_nWDOG_RST pin will result in the supervisor asserting X_PMIC_PWRON, which will in turn power cycle the PMIC and cause a reset by cycling power to the processor.
The supervisory circuit also monitors the voltage level of the VCC5V_IN input. When this supply drops below the set threshold (~4.6 V), the reset output is asserted until the voltage returns to a valid level above the threshold.
